1. Field of the Invention
The present invention relates to a signal adjusting system and related adjusting method, and more particularly to a memory system that reduces phase differences between a plurality of transmitted signals, and a related method.
2. Description of the Prior Art
In a memory system, the data signal transmitting between a controlling chipset and a memory is accomplished by data transmitting paths installed between the controlling chipset and the memory. For the transmitted data signal with a specific frequency, the transmitting path is just like a low pass filter. In other words, a data signal with different frequencies would have different transmitting times when transmitted through a transmitting path of the same length. Accordingly, if the data signals with different frequencies are transmitted with a synchronized phase at the starting end of the transmitting path, then the phases of the data signals will be asynchronous at the terminal end of the transmitting path. FIG. 1 is a timing diagram illustrating a conventional memory system which employs a transmitting path to transmit two data signals with different frequencies between the controlling chipset and the memory. For brevity, the frequency F1 of the first data signal s1 is faster than the frequency F2 of the second data signal s2. In addition, the phase of the first data signal s1 is synchronized with the phase of the second data signal s2 when the first data signal s1 and the second data signal s2 are transmitted by the memory at time t1. However, the controlling chipset receives the first data signal s1 and the second data signal s2 with different phases. This is because the first data signal s1 with the faster frequency would have a shorter transmission time through the transmitting path, and the second data signal s2 with the slower frequency would have a longer transmission time through the transmitting path. Therefore, the second data signal s2 is still being transmitted when the controlling chipset receives the first data signal s1 at time t2. The second data signal s2 is then received by the controlling chipset at time t3. Accordingly, the controlling chipset receives incorrect data from the first data signal s1 and the second data signal s2 since the first data signal s1 and the second data signal s2 are asynchronous. Providing an efficient way to solve the phase difference of the data signals emerging from the transmitting path between the controlling chipset and the memory is a significant concern in a memory system.